Logic simulation is a central aspect of the integrated circuit (IC) development process and serves as the primary tool for verifying a wide range of aspects in a design. Foremost among these aspects is the correctness of a design's functional behavior, both as a behavioral description of the system, as well as a structural (gate-level) description. Most industry design flows invest the largest fraction of their time and resources precisely on this task, in an attempt to provide the best possible guarantee that the system satisfies its original functional specification. Often large server farms comprising thousands of machines are employed for months at a time to execute billions of cycles of simulation. Much of this time is consumed in simulation of gate-level netlists, which involves large netlists at a fairly low-level description, comprising many components that must be simulated. Overall the simulation and verification of an integrated circuit design is one of the most time consuming tasks in the entire development process; and the performance limitations of logic simulators are one its main reasons. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon.
Logic simulation entails evaluating the response of an IC design over time when subjected to a set of input stimuli, typically selected by the designer to be representative of practical use situations. For most designs (synchronous), the response of the logic simulation is computed once for each cycle of simulated execution. Modern logic simulator implementations read in a design description, then “compile” the description to produce machine code emulating the same functionality as the design's primitives. Simulation finds application in many aspects of a design development process, including functional validation, power and timing estimation and checking of equivalence among different circuit representation. Gate-level netlists must be simulated for most of these applications.
Particularly problematic for logic simulators, however, is that simulation of structural netlists is a notoriously time-consuming process, yet essential to determine that if a synthesized design matches the initial design specifications and behavioral description. As circuit designs increase in size and features offered, they increase in complexity. As a result, there is an increasing need for improved performance by logic simulators for IC design.